1. Field of the Invention
The invention relates to a shift register, and more particularly to a shift register to realize prevention of malfunctions in the last stage flip-flop.
2. Description of the Related Art
Shift registers have been widely used in data driving circuits and gate driving circuits, for controlling timing in receiving data signals in each data line and for generating a scanning signal for each gate line, and the like. In a data driving circuit, a shift register outputs a selection signal so as to write an image signal into each data line. Meanwhile, in the gate driving circuit, the shift register outputs a scanning signal so as to sequentially write the image signal supplied to each data line into pixels in a pixel array.
FIG. 1 shows a conventional shift register. A pulse is shifted through the flip-flops in accordance with output signals of preceding flip-flops and feedback signals from following flip-flops. In other words, each output signal from the flip-flops is outputted as the set signal for the following flip-flop thereof, and inputted to the preceding flip-flop thereof as the reset signal for resetting the preceding flip-flop. Thus, the flip-flops that have outputted signals are reset as the pulse is shifted through the following flip-flops. Note that an output signal from a last-stage flip-flop F(N+1) is inputted to the preceding flip-flop F(N) and to itself as reset signals. Thus, it is necessary to stop (self-reset) operation of the last-stage flip-flop F(N+1) by using the output signal of itself. However, if there is some delay between the feedback signals of the flip-flops F(N+1) and F(N), the last-stage flip-flop F(N+1) would be reset (i.e. stopped) before the preceding flip-flop F(N), causing an abnormal output signal OUT(N) to be generated, such that the shift register malfunctions.
Therefore, a novel design of a shift register to realize prevention of malfunctions in the last stage flip-flop is highly required.